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| April 1998 ML4812* Power Factor Controller GENERAL DESCRIPTION The ML4812 is designed to optimally facilitate a peak current control boost type power factor correction system. Special care has been taken in the design of the ML4812 to increase system noise immunity. The circuit includes a precision reference, gain modulator, error amplifier, overvoltage protection, ramp compensation, as well as a high current output. In addition, start-up is simplified by an under-voltage lockout circuit with 6V hysteresis. In a typical application, the ML4812 functions as a current mode regulator. The current which is necessary to terminate the cycle is a product of the sinusoidal line voltage times the output of the error amplifier which is regulating the output DC voltage. Ramp compensation is programmable with an external resistor, to provide stable operation when the duty cycle exceeds 50%. FEATURES s s Precision buffered 5V reference (0.5%) Current-input gain modulator reduces external components and improves noise immunity Programmable ramp compensation circuit 1A peak current totem-pole output drive Overvoltage comparator helps prevent output voltage "runaway" Wide common mode range in current sense comparators for better noise immunity Large oscillator amplitude for better noise immunity s s s s s * Some Packages Are End Of Life BLOCK DIAGRAM (Pin Configuration Shown is for DIP Version) OVP 5 + SHDN S + - - 5V 1 - Q Q 10 ISENSE 5V VCC OUT 12 R 2 3 GM OUT EA OUT ERROR AMP UNDER VOLTAGE LOCKOUT IEA PWR GND 11 VREF VCC 4 EA- 5V 14 13 + - 32V 6 ISINE GAIN MODULATOR GND 15 7 16 RAMP COMP CT 5V CLOCK 9 8 RT OSC 1k 1 ML4812 PIN CONFIGURATION ML4812 16-Pin PDIP (P16) ISENSE GM OUT EA OUT EA- OVP ISINE RAMP COMP RT 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 CT GND VREF VCC OUT PWR GND SHDN CLOCK EA OUT EA- NC OVP ISINE 4 5 6 7 8 9 10 11 12 13 ML4812 20-Pin PLCC (Q20) GM OUT ISENSE GND NC 3 2 1 20 19 18 17 16 15 14 VREF VCC NC OUT PWR GND RAMP COMP CLOCK CT TOP VIEW TOP VIEW PIN DESCRIPTION PIN NAME FUNCTION PIN NAME FUNCTION 1 ISENSE Input from the current sense transformer to the non-inverting input of the PWM comparator. Output of gain modulator. A resistor to ground on this pin converts the current to a voltage. This pin is clamped to 5V and tied to the inverting input of the PWM comparator. Output of error amplifier. Inverting input to error amplifier. Input to over voltage comparator. Current gain modulator input. Buffered output from the oscillator ramp (CT). A resistor to ground sets the current which is internally subtracted from the product of ISINE and IEA in the gain modulator. 8 RT 2 GM OUT Oscillator timing resistor pin. A 5V source sets a current in the external resistor which is mirrored to charge CT. Digital clock output. A TTL compatible low level on this pin turns off the output. 9 10 11 CLOCK SHDN 3 4 5 6 7 EA OUT EA- OVP ISINE RAMP COMP PWR GND Return for the high current totem pole output. OUT VCC VREF GND CT High current totem pole output. Positive Supply for the IC. Buffered output for the 5V voltage reference. Analog signal ground. Timing capacitor for the oscillator. 12 13 14 15 16 2 SHDN NC RT ML4812 ABSOLUTE MAXIMUM RATINGS Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. Supply Current (ICC) ............................................... 30mA Output Current Source or Sink (OUT) DC ................ 1.0A Output Energy (capacitive load per cycle) .................. 5J Gain Modulator ISINE Input (ISINE) ......................... 1.2mA Error Amp Sink Current (EA OUT) .......................... 10mA Oscillator Charge Current ........................................ 2mA Analog Inputs (ISENSE, EA-, OVP) .............. -0.3V to 5.5V Junction Temperature ............................................. 150C Storage Temperature Range ..................... -65C to 150C Lead Temperature (soldering 10 sec.) ..................... 260C Thermal Resistance (JA) 20-Pin PLCC .................................................... 60C/W 16-Pin PDIP ..................................................... 65C/W OPERATING CONDITIONS Temperature Range ML4812CX ............................................... 0C to 70C ML4812IX ............................................. -40C to 85C ELECTRICAL CHARACTERISTICS Unless otherwise specified, VCC = 15V , RT = 14k, CT = 1000pF, TA = Operating Temperature Range (Notes 1, 2). PARAMETER OSCILLATOR Initial Accuracy Voltage Stability Temperature Stability Total Variation Ramp Valley to Peak RT Voltage Discharge Current (RT open) Clock Out Voltage Low Clock Out Voltage High REFERENCE Output Voltage Line Regulation Load Regulation Temperature Stability Total Variation Output Noise Voltage Long Term Stability Short Circuit Current ERROR AMPLIFIER Input Offset Voltage Input Bias Current Open Loop Gain PSRR Output Sink Current Output Source Current Output High Voltage Output Low Voltage Unity Gain Bandwidth 1 < VEA OUT < 5V 12V < VCC < 25V VEA OUT = 1.1V, VEA- = 6.2V VEA OUT = 5.0V, VEA- = 4.8V IEA OUT = -0.5mA, VEA- = 4.8V IEA OUT = 1mA, VEA- = 6.2V 60 60 2 -0.5 5.3 -0.1 75 75 12 -1.0 5.5 0.5 1.0 1.0 15 -1.0 mV A dB dB mA mA V V MHz Line, load, temp. 10Hz to 10kHz TJ = 125C, 1000 hours VREF = 0V -30 4.9 50 5 -85 25 -180 TJ = 25C, IO = 1mA 12V < VCC < 25V 1mA < IO < 20mA 4.95 5.00 2 2 0.4 5.1 5.05 20 20 V mV mV % V V mV mA TJ = 25C, VCT= 2V VCT = 2V RL = 16k RL = 16k 3.0 4.8 7.8 7.3 Line, temperature 90 3.3 5.0 8.4 8.4 0.2 3.5 5.2 9.0 9.3 0.5 TJ = 25C 12V < VCC < 18V 91 98 0.3 2 108 105 kHz % % kHz V V mA mA V V CONDITIONS MIN TYP MAX UNITS 3 ML4812 ELECTRICAL CHARACTERISTICS (Continued) PARAMETER GAIN MODULATOR ISINE Input Voltage Output Current (GM OUT) ISINE = 500A ISINE = 500A, EA- = VREF -20mV ISINE = 500A, EA- = VREF + 20mV ISINE = 1mA, EA- = VREF - 20mV ISINE = 500A, EA- = VREF - 20mV, IRAMP COMP = 50A Bandwidth PSRR OVP COMPARATOR Input Offset Voltage Hysteresis Input Bias Current Propagation Delay PWM COMPARATOR: ISENSE Input Offset Voltage Input Offset Current Input Common Mode Range Input Bias Current Propagation Delay ILIMIT Trip Point OUTPUT Output Voltage Low IOUT = -20mA IOUT = -200mA Output Voltage High IOUT = 20mA IOUT = 200mA Output Voltage Low in UVLO Output Rise/Fall Time Shutdown IOUT = -5mA, VCC = 8V CL = 1000pF VIH VIL IIL, VSHDN = 0V IIH, VSHDN = 5V UNDER-VOLTAGE LOCKOUT Startup Threshold Shutdown Threshold VREF Good Threshold SUPPLY Supply Current Start-Up, VCC = 14V, TJ = 25C Operating, TJ = 25C Internal Shunt Zener Voltage ICC = 30mA 25 0.8 20 30 1.2 25 34 mA mA V 15 9 16 10 4.4 17 11 V V V 2.0 0.8 -1.5 10 13 12 0.1 1.6 13.5 13.4 0.1 50 0.8 0.4 2.2 V V V V V ns V V mA A VGM OUT = 5.5V 4.8 -0.2 -2 150 5 5.2 15 1 5.5 -10 mV A V A ns V Output Off Output On -25 95 105 -0.3 150 +5 115 -3 mV mV A ns 12V < VCC < 25V 860 0.4 430 0.7 470 3 940 455 200 70 0.9 510 10 1020 V A A A A kHz dB CONDITIONS MIN TYP MAX UNITS Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions. Note 2: VCC is raised above the Startup Threshold first to activate the IC, then returned to 15V. 4 ML4812 FUNCTIONAL DESCRIPTION OSCILLATOR The ML4812 oscillator charges the external capacitor (CT) with a current (ISET) equal to 5/RSET. When the capacitor voltage reaches the upper threshold, the comparator changes state and the capacitor discharges to the lower threshold through Q1. While the capacitor is discharging, Q2 provides a high pulse. The Oscillator period can be described by the following relationship: TOSC = TRAMP + TDEADTIME where: VOUT = VIN 1 - D ON C T VRAM P VALLEY TO PEAK 8.4mA - I SET and: TDEADTIM E = 10 8 10nF EXTERNAL CLOCK CSYNC 10 90% 5nF 2nF 1nF 85% MAXIMUM DUTY CYCLE (%) 5 80% SYNC Q2 RT 9 RT (k) 3 70% 20nF 2 ISET RSYNC RT 16 CT 8.4mA ISET + CT 1 10 100 OSCILLATOR FREQUENCY (kHz) 1000 5.6V - Q1 Figure 2. Oscillator Timing Resistance vs. Frequency 15 OUTPUT SATURATION VOLTAGE (V) CLOCK tD RAMP PEAK V(CT) RAMP VALLEY VCC 14 13 VCC = 15V 80s PULSED LOAD 120Hz RATE SOURCE SATURATION LOAD TO GROUND SINK SATURATION LOAD TO VCC 3 2 1 Figure 1. Oscillator Block Diagram GND 0 0 200 400 600 800 OUTPUT CURRENT (mA) Figure 3. Output Saturation Voltage vs. Output Current 5 ML4812 FUNCTIONAL DESCRIPTION (Continued) OUTPUT DRIVER STAGE The ML4812 output driver is a 1A peak output high speed totem pole circuit designed to quickly drive capacitive loads, such as power MOSFET gates. (Figure 3) ERROR AMPLIFIER The ML4812 error amplifier is a high open loop gain, wide bandwidth, amplifier.(Figures 4-5) GAIN MODULATOR The ML4812 gain modulator is of the current-input type to provide high immunity to the disturbances caused by high power switching. The rectified line input sine wave is converted to a current via a dropping resistor. In this way, small amounts of ground noise produce an insignificant effect on the reference to the PWM comparator. The output of the gain modulator is a current of the form: IOUT is proportional to ISINE x IEA, where ISINE is the current in the dropping resistor, and IEA is a current proportional to the output of the error amplifier. When the error amplifier is saturated high, the output of the gain modulator is approximately equal to the ISINE input current. The gain modulator output current is converted into the reference voltage for the PWM comparator through a resistor to ground on the gain modulator output. The gain modulator output is clamped to 5V to provide current limiting. Ramp compensation is accomplished by subtracting 1/2 of the current flowing out of RAMP COMP through a buffer transistor driven by CT which is set by an external resistor. UNDER VOLTAGE LOCKOUT On power-up the ML4812 remains in the UVLO condition; output low and quiescent current low. The IC becomes operational when VCC reaches 16V. When VCC drops below 10V, the UVLO condition is imposed. During the UVLO condition, the 5V VREF pin is "off", making it usable as a "flag" for starting up a downstream PWM converter. ERROR CURRENT ISINE 9V ISINE x ERROR CURRENT - IRAMP COMP/2 5V + 0.5mA 8V 6 EA- 4 - GM OUT 2 RAMP COMP 7 16 CT 5V EA OUT 3 IRAMP COMP Figure 4. Error Amplifier Configuration 100 0 Figure 6. Gain Modulator Block Diagram 500 4.5 ERROR AMP OUTPUT VOLTAGE (V) MULTIPLE OUTPUT CURRENT (A) 80 -30 AVOL, OPEN LOOP GAIN (dB) 400 4.0 3.5 EXCESS PHASE (degrees) 60 PHASE -60 300 40 -90 3.0 200 2.5 100 2.0 1.5 20 GAIN 0 -120 -150 -20 10 100 1k 10k 100k 1M -180 10M 0 0 100 200 300 400 500 FREQUENCY (Hz) SINE INPUT CURRENT (A) Figure 5. Error Amplifier Open-Loop Gain and Phase vs Frequency Figure 7. Gain Modulator Linearity 6 ML4812 TYPICAL APPLICATIONS INPUT INDUCTOR (L1) SELECTION The central component in the regulator is the input boost inductor. The value of this inductor controls various critical operational aspects of the regulator. If the value is too low, the input current distortion will be high and will result in low power factor and increased noise at the input. This will require more input filtering. In addition, when the value of the inductor is low the inductor dries out (runs out of current) at low currents. Thus the power factor will decrease at lower power levels and/or higher line voltages. If the inductor value is too high, then for a given operating current the required size of the inductor core will be large and/or the required number of turns will be high. So a balance must be reached between distortion and core size. One more condition where the inductor can dry out is analyzed below where it is shown to be maximum duty cycle dependent. For the boost converter at steady state: SUPPLY CURRENT (mA) 25 20 ICC (mA) 15 10 5 0 0 10 20 VCC (V) 30 40 Figure 9a. Total Supply Current vs. Supply Voltage 25 VOUT = VIN 1- D ON 20 (1) OPERATING CURRENT Where DON is the duty cycle [TON/(TON + TOFF)]. The input boost inductor will dry out when the following condition is satisfied: 15 10 VIN(t ) < VOUT (1- D ON ) or VIND RY = [1 - D ON (max)] VOUT (2) 5 STARTUP (3) 0 -60 -40 -20 0 20 40 60 80 100 120 140 VINDRY: voltage where the inductor dries out. VOUT: output DC voltage. Effectively, the above relationship shows that the resetting volt-seconds are more than setting volt-seconds. In energy transfer terms this means that less energy is stored in the inductor during the ON time than it is asked to deliver during the OFF time. The net result is that the inductor dries out. 0 TEMPERATURE (degrees) Figure 9b. Supply Current (ICC) vs. Temperature -4 -8 VREF (mV) 5V VREF 9V - + INTERNAL BIAS VCC -12 ENABLE VREF VREF GEN. -16 -20 -24 0 20 40 60 IREF (mA) 80 100 120 Figure 8. Under-Voltage Lockout Block Diagram Figure 10. Reference Load Regulation 7 ML4812 TYPICAL APPLICATIONS (Continued) The recommended maximum duty cycle is 95% at 100KHz to allow time for the input inductor to dump its energy to the output capacitors. For example, if: VOUT = 380V and DON (max) = 0.95, then substituting in (3) yields VINDRY = 20V. The effect of drying out is an increase in distortion at low voltages. For a given output power, the instantaneous value of the input current is a function of the input sinusoidal voltage waveform, i.e. as the input voltage sweeps from zero volts to a maximum value equal to its peak so does the current. The load of the power factor regulator is usually a switching power supply which is essentially a constant power load. As a result, an increase in the input voltage will be offset by a decrease in the input current. By combining the ideas set forth above, some ground rules can be obtained for the selection and design of the input inductor: Step 1: Find minimum operating current. The inductor can be allowed to decrease in value when the current sweeps from minimum to maximum value. This allows the use of smaller core sizes. The only requirement is that the ramp compensation must be adequate for the lower inductance value of the core so that there is adequate compensation at high current. Step 4: The presence of the ramp compensation will change the dry out point, but the value found above can be considered a good starting point. Based on the amount of power factor correction the above value of L1 can be optimized after a few iterations. Gapped Ferrites, Molypermalloy, and Powdered Iron cores are typical choices for core material. The core material selected should have a high saturation point and acceptable losses at the operating frequency. One ferrite core that is suitable at around 200W is the #4119PL00-3C8 made by Philips Components (Ferroxcube). This ungapped core will require a total gap of 0.180" for this application. OSCILLATOR COMPONENT SELECTION The oscillator timing components can be calculated by using the following expression: fOSC = 136 . RT CT IIN(min)PEAK = 1414 PIN(min) . VIN(max) (4) VIN(max) = 260V PIN(min) = 50W then: IIN(min)PEAK = 0.272A Step 2: Choose a minimum current at which point the inductor current will be on the verge of drying out. For this example 40% of the peak current found in step 1 was chosen. then: ILDRY = 100mA Step 3: The value of the inductance can now be found using previously calculated data. L1 = VIND RY D ON (max) ILD RY fOSC 20 V 0.95 = = 2mH 100mA 100KHz (6) For example: Step 1: At 100kHz with 95% duty cycle TOFF = 500ns calculate CT using the following formula: CT = TOFF IDIS = 1000pF VOSC (7) Step 2: Calculate the required value of the timing resistor. RT = 136 . 136 . = fOSC C T 100KHz 1000pF = 136kW choose R T = 14kW . (8) (5) 8 ML4812 TYPICAL APPLICATIONS (Continued) CURRENT SENSE AND SLOPE (RAMP) COMPENSATION COMPONENT SELECTION Slope compensation in the ML4812 is provided internally. Rather than adding slope to the noninverting input of the PWM comparator, it is actually subtracted from the voltage present at the inverting input of the PWM comparator. The amount of slope compensation should be at least 50% of the downslope of the inductor current during the off time, as reflected to the inverting input of the PWM comparator. Note that slope compensation is required only when the inductor current is continuous and the duty cycle is more than 50%. The downslope of the inductor current at the verge of discontinuity can be found using the expression given below: diL VOUT - VIN DRY 380 V - 20V = = = 0.18 A / ms (9) 2mH dt L RM = VCLAMP R P 49 750k . = = 288k . 90 1414 . VIN (PEAK) (13) The peak of the inductor current can be found approximately by: ILPEAK = 1414 POUT 1414 200 . . = = 314A . 90 VIN (RM S ) (14) Selection of NC which depends on the maximum switch current, assume 4A for this example is 80 turns. RS = VCLAM P NC 4.9 80 = = 100W 4 ILPEAK (15) The downslope as reflected to the input of the PWM comparator is given by: S PWM = S PWM = VOUT - VIN DRY L RS NC Where RS is the sense resistor, and VCLAMP is the current clamp at the inverting input of the PWM comparator. This clamp is internally set to 5V. In actual application it is a good idea to assume a value less than 5V to avoid unwanted current limiting action due to component tolerances. In this application, VCLAMP was chosen as 4.9V. Having calculated RS, the value SPWM and of RSC can now be calculated: 25 R M . R SC = A SC S PWM R T C T (16) 25 28.8k . = 33k R SC = 6 0.7 (0.225 10 ) 14K 1 nF The following values were used in the calculation: RM = 28.8k RT = 14k ASC = 0.7 CT = 1nF (10) 380 V - 20 100 = 0.225V / ms 2mH 80 Where RS is the current sense resistor and NC is the turns ratio of the current transformer (T1) used. In general, current transformers simplify the sensing of switch currents (especially at high power levels where the use of sense resistors is complicated by the amount of power they have to dissipate). Normally the primary side of the transformer consists of a single turn and the secondary consists of several turns of either enameled magnet wire or insulated wire. The diameter of the ferrite core used in this example is 0.5" (SPANG/Magnetics F41206-TC). The rectifying diode at the output of the current transformer can be a 1N4148 for secondary currents up to 75mA average. Sense FETs or resistive sensing can also be used to sense the switch current. The sensed signal has to be amplified to the proper level before it is applied to the ML4812. The value of the ramp compensation (SCPWM) as seen at the inverting terminal of the PWM comparator is: SC PWM = 25 R M . R T C T R SC VOLTAGE REGULATION COMPONENTS The values of the voltage regulation loop components are calculated based on the operating output voltage. Note that voltage safety regulations require the use of sense resistors that have adequate voltage rating. As a rule of thumb if 1/4W resistors are chosen, two of them should be used in series. The input bias current of the error amplifier is approximately 0.5A, therefore the current available from the voltage sense resistors should be significantly higher than this value. Since two 1/4W resistors have to be used the total power rating is 1/2W. The operating power is set to be 0.4W then with 380V output voltage the value can be calculated as follows: R 1 = ( 380V) 2 / 0.4W = 360k (11) (17) The required value for RSC can therefore be found by equating: SCPWM = ASC x SPWM, where ASC is the amount of slope compensation and solving for RSC. The value of GM OUT depends on the selection of RAMP COMP. RP = VIN (max) PEAK 260 1414 . = = 750k 0.5mA I SINE (PEAK) (12) Choose two 178k, 1% connected in series. Then R2 can be calculated using the formula below: VREF R 1 5V 356k = = 4747k . R2 = (18) 380V - 5V VOUT - VREF 9 ML4812 TYPICAL APPLICATIONS (Continued) Choose 4.75k, 1%. One more critical component in the voltage regulation loop is the feedback capacitor for the error amplifier. The voltage loop bandwidth should be set such that it rejects the 120Hz ripple which is present at the output. If this ripple is not adequately attenuated it will cause distortion on the input current waveform. Typical bandwidths range anywhere from a few Hertz to 15Hz. The main compromise is between transient response and distortion. The feedback capacitor can be calculated using the following formula: 1 3142 R 1 BW . 1 = 0.44mF CF = 3142 356k 2Hz . CF = The values of the start-up resistor R10 and capacitor C15 may need to be optimized depending on the application. The charging waveform for the secondary winding of L1 is an inverted chopped sinusoid which reaches its peak when the line voltage is at its minimum. In this example, C9 = 0.1F, C15 = 330F, D8 = 1N4148, R10 = 39k, 2W. ENHANCEMENT CIRCUIT The power factor enhancement circuit shown in Figure 12 is described in detail in Application Note 11. It improves the power factor and lowers the input current harmonics. Note that the circuit meets IEC 1000-3-2 specifications (with the enhancement) on the harmonics by a large margin while correcting the input power factor to better than 0.99 under most steady state operating conditions. CONSTRUCTION AND LAYOUT TIPS High frequency power circuits require special care during breadboard construction and layout. Double sided printed circuit boards with ground plane on one side are highly recommended. All critical switching leads (power FET, output diode, IC output and ground leads, bypass capacitors) should be kept as small as possible. This is to minimize both the transmission and pick-up of switching noise. There are two kinds of noise coupling; inductive and capacitive. As the name implies inductive coupling is due to fast changing (high di/dt) circulating switching currents. The main source is the loop formed by Q1, D5, and C3-C4. Therefore this loop should be as small as possible, and the above capacitors should be good high frequency types. The second form of noise coupling is due to fast changing voltages (high dv/dt). The main source in this case is the drain of the power FET. The radiated noise in this case can be minimized by insulating the drain of the FET from the heatsink and then tying the heatsink to the source of the FET with a high frequency capacitor (CH in Figure 12). The IC has two ground pins named PWR GND and Signal GND. These two pins should be connected together with a very short lead at the printed circuit board exit point. In general grounding is very important and ground loops should be avoided. Star grounding or ground plane techniques are preferred. (19) OVERVOLTAGE PROTECTION (OVP) COMPONENTS The OVP loop should be set so that there is no interaction with the voltage control loop. Typically it should be set to a level where the power components are safe to operate. Ten to fifteen volts above VOUT is generally a good setpoint. This sets the maximum transient output voltage to about 395V. By choosing the high voltage side resistor of the OVP circuit the same way as above i.e. R4 = 356K then R5 can be calculated as: R5 = VREF R 4 5V 356k = = 4564k . 395V - 5V VOVP - VREF (20) Choose 4.53k, 1%. Note that R1, R2, R4 and R5 should be tight tolerance resistors such as 1% or better. CONTROLLER SHUTDOWN The ML4812 provides a shutdown pin which could be used to shutdown the IC. Care should be taken when this pin is used because power supply sequencing problems could arise if another regulator with its own bootstrapping follows the ML4812. In such a case a special circuit should be used to allow for orderly start up. One way to accomplish this is by using the reference voltage of the ML4812 to inhibit the other controller IC or to shut down its bias supply current. OFF-LINE START-UP AND BIAS SUPPLY GENERATION The ML4812 can be started using a "bleed resistor" from the high voltage bus. After the voltage on VCC exceeds 16V, the IC starts up. The energy stored on the 330F, C15, capacitor supplies the IC with running power until the supplemental winding on L1 can provide the power to sustain operation. 10 ML4812 TYPICAL APPLICATIONS (Continued) MATERIAL Powdered Iron Powdered Iron Molypermalloy MANUFACTURER Micrometals Micrometals SPANG (Mag. Inc.) PART # T225-8/90 T184-40 58076-A2 (high flux) TURNS (#24AWG) 200 120 180 Table 1. Toroidal Cores (L1) MAGNETICS TIPS L1 -- Main Inductor As shown in Table 1, one of several toroidal cores can be used for L1. The T184-40 core above is the most economical, but has lower inductance at high current. This would yield higher ripple current and require more line EMI filtering. The value for RSC (slope compensation resistor on RAMP COMP) was calculated for the T225-8/ 90 and should be recalculated for other inductor characteristics. The various core manufacturers have a range of applications literature available. A gapped ferrite core can also be used in place of the powdered iron core. One such core is a Philips Components (Ferroxcube) core #4229PL00-3C8. This is an ungapped core. Using 145 turns of #24 AWG wire, a total air gap of 0.180" is required to give a total inductance of about 2mH. Since 1/2 of the gap will be on the outside of the core and 1/2 the gap on the inside, putting a 0.09" spacer in the center will yield a 0.180" total gap. To prevent leakage fields from generating RFI, a shorted turn of copper tape should be wrapped around the gap as shown in Figure 11. For production, a gapped center leg can be ordered from most core vendors, eliminating the need for the external shorted copper turn when using a potentiometer core. T1 -- Sense Transformer In addition to the core type mentioned in the parts list, the following Siemens cores should be suitable for substitution and may be more readily available in Europe. MATERIAL N27 N30 SIZE CODE R16/6.3 R16/6.3 PART # B64290-K45-X27 B64290-K45-X830 The N27 material is for high frequency and will work better above 100KHz but both are adequate. In addition, Philips Components (Ferroxcube) core 768T188-3C8 can be used. Please also refer to the list of core vendors below SPANG/Magnetics Inc. Micrometals Philips Components 1 (800) 245-3984, or (412) 282-8282 1 (800) 356-5977 (914) 247-2064 COPPER FOIL SHORTED TURN 0.09" GAP Figure 11. Copper Foil Shorted Turn 11 12 D10 1N5406 D9 7812 + 330F 25V 1F - VCC + C10 OPTIONAL ENHANCEMENT CKT. R1A 180k R10 39k 2W NS L1 1 R12 1K Q3 C19 R1B 180k R4B 180k RPB 150k C17 D12 IC1 CF 22k D3 1N5406 R3 CT 2nF D11 D13 R11 33k C11 1nF RS 100 B R6 150k 1W R4A 180k RPA 360k A + R13 22k D2 1N5406 D6 T1 NP 2 C18 D5 MUR850 C3 6.8nF 1kV C4 1F 630V D1 1N5406 C16 + 100F 25V P3* C15 Q2 D8 OFF-LINE START-UP AND BIAS SUPPLY C5 680F 200V P2 + VOUT RG 10 Q1 R7 150k 1W *** C9 0.1F C8 0.1F IRF840 HEATSINK CH 6.8nF - C6 680F 200V 380 VDC C1 1F 630V ML4812 FUSE F1 5A 250V P1 L 90 TO 260 VAC AC IN N 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 R5A 10k RSC 33k R5B 3.9k ML4812 RT 7.5k R2A 10k D4 1N5406 RGMOUT 27k R2B 3.9k ** SEE NOTES BELOW * P3 IS USED AT INITAL TURN-ON TO CHECK THE IC FOR PROPER OPERATION. APPLY 16VDC. ** Figure 12. Typical Application, 200W Power Factor Correction Circuit *** NOTES: 1. ALL UNSPECIFIED DIODES ARE 1N4148. 2. ALL UNSPECIFIED RESISTORS ARE 1/4 WATT. 3. ALL UNSPECIFIED CAPACITOR VOLTAGE RATINGS ARE 50V. 4. ADJUST R2A AND R5A WITH CAUTION TO AVOID OVER VOLTAGE CONDITIONS. Q3 = 2N2222 OR EQUIVALENT. FIXED RESISTORS CAN BE USED FOR THE SENSING COMPONENTS. BELOW ARE 1% STANDARD RESISTORS THAT WILL FORCE THE CORRECT OUTPUT VOLTAGES R1A, R1B, R4A, R4B = 178k 1%, R2B = 4.75 1%, R5B = 4.53k 1%. USE JUMPERS INSTEAD OF R2A AND R5A (POTS). FOR HIGHER POWER USE MORE VCC DECOUPLING. 2F OR MORE BE REQUIRED AT 1KW LEVELS. ML4812 REFERENCE C1, C4 C3, CH C5, C6 C8, C9 C10, C19 C11 C15 C16 C17 CF CT D1, D2, D3, D4, D10 D5 D6, D8, D9 D11, D12, D13 F1 IC1 L1 Q1 Q2 Q3 DESCRIPTION 1F, 630V Film (250VAC) 6.8nF, 1KV Ceramic disk 680F, 200V Electrolytic 0.1F, 50V Ceramic 1F, 50V Ceramic 0.001F, 50V Ceramic 330F, 25V Electrolytic 100F, 25V Electrolytic 10F, 25V Electrolytic 0.47F, 50V Ceramic 0.002F, 50V Ceramic 1N5406 (Motorola) MUR850 (Motorola) 1N4148 5A, 250V 3AG with clips ML4812CP (Micro Linear) 2mH, 4A IPEAK (see note) IRF840 or MTPN8N50 LM7815CT 2N2222 or equivalent REFERENCE R1A, R1B, R4A, R4B R2A, R5A R2B, R5B R3, R13 R6, R7, RPB R10 R11 R12 RG RM RPA, R15 RS RSC RT T1 Notes: DESCRIPTION 180k 10k TRIMPOT BOURNS 3299 or equivalent 3.9k 22k 150k 39k, 2W 33k 1k 10 27k 360k 100k 33k 7.5k SPANG F41206-TC NS = 80, NP = 1 (see note) All resistors 1/4W unless otherwise specified. Some reference designators are skipped (e.g. C2, C12, etc.) and do not appear on the schematic. These designators were used in previous revisions of the board and are not used on this revision. Additional information on key components is included in the attached appendix. Table 2. Component Values/Bill of Materials for Figure 12 13 14 VCC 2N2222 Q3 + 330K GND D1 1N5406 D4 R1A 180K 22K VCC *** IC1 BRIDGE RECTIFIER CF GND C3 C2 C1 1F 1F 1F 500V 500V 500V C6 1F C14 1F CT 2.2nF R1B 180K R4B 180K RPB 150K R7 R3 33K C5 1nF 1T R4 150K 1W RS 22 80T R4A 360K RPA 360K T1 C8 15F 630V L1 566H D5 MUR3050 22K R6 C13 10F D2 VZ 3.5V R1 ENHANCEMENT CIRCUIT SEE TEXT R2 ML4812 FUSE F1 + L 15A 250V C9 15F 630V C12 1F 630V GND C10 680F 250V VOUT C11 680F 250V AC IN R5 150K Q1 Q2 APT5025 APT5025 1W RG1 3 RG2 3 R2A 5K RSC 51K RM 27K ** R2B 3K R5B 3K R5A 5K ML4812 RT 6.2K 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 C4 0.1F C7 0.1F N - * AT INITIAL TURN-ON TO CHECK THE IC FOR PROPER OPERATION, APPLY 16VDC. ** Figure 13. 1kW Input Power, Power Factor Correction Circuit *** NOTES: 1. ALL UNSPECIFIED DIODES ARE 1N4148. 2. ALL UNSPECIFIED RESISTORS ARE 1/4 WATT. 3. ALL UNSPECIFIED CAPACITOR VOLTAGE RATINGS ARE 50V. 4. ADJUST R2A AND R5A WITH CAUTION TO AVOID OVER VOLTAGE CONDITIONS. Q3 = 2N2222 OR EQUIVALENT. FIXED RESISTORS CAN BE USED FOR THE SENSING COMPONENTS. BELOW ARE 1% STANDARD RESISTORS THAT WILL FORCE THE CORRECT OUTPUT VOLTAGES R1A, R1B, R4A, R4B = 178k 1%, R2B = 4.75 1%, R5B = 4.53k 1%. USE JUMPERS INSTEAD OF R2A AND R5A (POTS). FOR HIGHER POWER USE MORE VCC DECOUPLING. ML4812 PHYSICAL DIMENSIONS inches (millimeters) Package: P16 16-Pin PDIP 0.740 - 0.760 (18.79 - 19.31) 16 PIN 1 ID 0.240 - 0.260 0.295 - 0.325 (6.09 - 6.61) (7.49 - 8.26) 0.02 MIN (0.50 MIN) (4 PLACES) 1 0.055 - 0.065 (1.40 - 1.65) 0.100 BSC (2.54 BSC) 0.015 MIN (0.38 MIN) 0.170 MAX (4.32 MAX) 0.125 MIN (3.18 MIN) 0.016 - 0.022 (0.40 - 0.56) SEATING PLANE 0 - 15 0.008 - 0.012 (0.20 - 0.31) Package: Q20 20-Pin PLCC 0.385 - 0.395 (8.89 - 10.03) 0.350 - 0.356 (8.89 - 9.04) 1 0.042 - 0.056 (1.07 - 1.42) 0.025 - 0.045 (0.63 - 1.14) (RADIUS) 0.042 - 0.048 (1.07 - 1.22) 6 PIN 1 ID 16 0.350 - 0.356 (8.89 - 9.04) 0.385 - 0.395 (8.89 - 10.03) 0.200 BSC (5.08 BSC) 0.290 - 0.330 (7.36 - 8.38) 11 0.050 BSC (1.27 BSC) 0.026 - 0.032 (0.66 - 0.81) 0.165 - 0.180 (4.19 - 4.57) 0.146 - 0.156 (3.71 - 3.96) 0.009 - 0.011 (0.23 - 0.28) 0.100 - 0.110 (2.54 - 2.79) 0.013 - 0.021 (0.33 - 0.53) SEATING PLANE 15 ML4812 ORDERING INFORMATION PART NUMBER ML4812CP ML4812CQ ML4812IP ML4812IQ TEMPERATURE RANGE 0C to 70C 0C to 70C -40C to 85C -40C to 85C PACKAGE Molded PDIP (P16) Molded PLCC (Q20) (End Of Life) Molded PDIP (P16) (End Of Life) Molded PLCC (Q20) (End Of Life) (c) Micro Linear 1998. is a registered trademark of Micro Linear Corporation. All other trademarks are the property of their respective owners. Products described herein may be covered by one or more of the following U.S. patents: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; 5,652,479; 5,661,427; 5,663,874; 5,672,959; 5,689,167; 5,714,897; 5,717,798. Japan: 2,598,946; 2,619,299; 2,704,176. Other patents are pending. Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design. Micro Linear does not assume any liability arising out of the application or use of any product described herein, neither does it convey any license under its patent right nor the rights of others. The circuits contained in this data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to whether the illustrated circuits infringe any intellectual property rights of others, and will accept no responsibility or liability for use of any application herein. The customer is urged to consult with appropriate legal counsel before deciding on a particular application. 2092 Concourse Drive San Jose, CA 95131 Tel: (408) 433-5200 Fax: (408) 432-0295 www.microlinear.com DS4812-01 1 |
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